The present invention relates to a cache control device and method for, in an information processing device having a cache, degenerating the cache by means of hardware.
In a prior art cache control system, there are a method of performing degeneration by hardware and a method of performing degeneration by operating system software (OS).
FIG. 1 is a block diagram showing a prior art main frame structure as an example of hardware control. In the drawing, the main frame comprises a central processing unit (hereafter referred to as a CPU) 11 and a memory system 12. The CPU 11 includes a CPU core 13 and a cache 14 which are the command control section. The cache 14 is designed as a four-way set associative cache comprising four cache ways 141 to 144. The memory system 12 is provided with a memory control unit (MCU) 15 and memory 16.
The cache 14 is a high integration memory device, therefore bit errors can easily occur due to alpha rays. If the number of one-bit errors exceeds a set value, the way including the section where the bit error occurred or the cache 14 is disconnected before a multiple bit error can occur. However, in a store-in type cache, the cache data must firstly be flushed to the memory. Thereafter, the cache does not store new data in the way where the errors occurred. This series of operations is called cache degeneration.
In a main frame structure, degeneration control requests from the cache 14 are sent to the MCU 15, and the MCU 15 flushes data from the cache 14 into the memory 16. In a main frame in which the CPU 11, including the cache 14, and the memory system 12 have been basically simultaneously designed and developed, the operating specifications of the cache 14 and memory system 12 have been determined simultaneously, therefore degeneration control can also be performed from the MCU 15.
FIG. 2 is a block diagram illustrating cache degeneration in a prior art open system, as an example of software control. This example is of a case where cache degeneration control is performed by an operating system (OS) operated by software or firmware.
Specifically, if a one bit error occurs, it is reported to the software, and the software initiates degeneration control in response thereto. For example, if data from all ways in the cache are flushed by such software control, the OS firstly issues the read addresses of data not existing in the cache to create a cache miss. As a result, although the OS accesses the memory 26 and reads the data therein, in a store-in type cache, before writing the content of the memory 26 into the cache in order to update the data within the cache, the data from the way that includes the least recently used data (LRU) existing in the cache 24 must be flushed to the memory 26. For example, even in the case of a one bit error occurring, the data read out from the cache is corrected by an ECC circuit. In this way the data in the cache is flushed to memory and the content of the memory updated prior to cache degeneration.
FIG. 3 is a block diagram illustrating cache degeneration in a multiprocessor system having a plurality of CPU cores 33 and 34 with respect to one cache 35. In this drawing, the multiprocessor system comprises a multiprocessor chip 31 and a memory system 32.
When the cache degeneration operation is performed, a cache degeneration request is issued via software from one of the CPU cores 33, and because the other CPU core 34 cannot access the cache, that CPU core must be placed in a suspended state. However, in order for the software to do this, it is necessary for there to be a software command for suspending either one of the CPU cores so that it does not access the cache; if there is no such command, it is difficult to completely flush the cache data.
When simultaneously developing a CPU 11 and memory system 12 as in a mainframe, there are no problems associated with conforming the operating specifications of the cache 14 and memory 16, so the cache can be flushed from the system side (MCU).
However, in an open system, because the CPU21 and memory system 22 are designed and developed separately, different CPUs may be mounted in the same memory system, or conversely the same CPUs may be mounted in different memory systems. In recent years, there has been a tendency for the operating frequencies of CPUs to gradually increase, thus the difference in CPU operating frequencies with respect to memory system and I/O operating frequencies has widened, and conversion of CPUs to faster models is repeatedly performed.
In open systems which have been developed with a view to operating under memory systems of a variety of scales, the memory system does not control the flushing of the cache, rather this is most often performed by the OS software.
In order to perform degeneration operations by means of the OS as above, the software or firmware must determine the cache structure, i.e. the cache size and number of ways. Also, where the cache is flushed by software, the cache control section must know by what algorithm the way from which the cache data is to be flushed must be selected.
That is, as described above, where only the CPU 21 is changed, without the memory system 22 being changed, the software or firmware must be changed when the cache size, number of ways and cache control algorithm of the CPU are changed, creating complex problems.
Further, in the case of a structure where a plurality of CPU cores share one cache as in the multiprocessor system shown in FIG. 3, when flushing data within the cache 35 to the memory system 32 by means of software or firmware, while data from the cache 35 is being flushed in response to a command from one CPU core 33, the other CPU core 34 must inhibit commands so that no effective data is passed to the cache 35.
However, in architecture which cannot issue a transition instruction to a wait state so that the CPU core inhibits commands, by means of software or firmware, since command inhibition control is not possible, as a result complete flushing of the cache data is difficult, hence the problem that degeneration of the cache is impossible.
In other words, in the case of architecture which cannot issue an instruction to a wait state so that a CPU core inhibits the issuance of commands, while one CPU core 33 is degeneration controlling the cache 35 via software, the other CPU core 34 could conceivably be accessing the memory. Hence, when performing degeneration which prohibits usage after flushing to the memory has finished, the data of a request from the other CPU core may also be stored in the way which must be degenerated.